Non-volatile memory cells are well known in the art. One prior art non-volatile split gate memory cell 10 is shown in FIG. 1. The memory cell 10 comprises a semiconductor substrate 12 of a first conductivity type, such as P type. The substrate 12 has a surface on which there is formed a first region 14 (also known as the source line SL) of a second conductivity type, such as N type. A second region 16 (also known as the drain line) also of N type is formed on the surface of the substrate 12. Between the first region 14 and the second region 16 is a channel region 18. A bit line BL 20 is connected to the second region 16. A word line WL 22 is positioned above a first portion of the channel region 18 and is insulated therefrom. The word line 22 has little or no overlap with the second region 16. A floating gate FG 24 is over another portion of the channel region 18. The floating gate 24 is insulated therefrom, and is adjacent to the word line 22. The floating gate 24 is also adjacent to the first region 14. A coupling gate CG (also known as control gate) 26 is over the floating gate 24 and is insulated therefrom. A SL poly 28 is connected to the first region 14 (source line SL).
In the prior art, various combinations of positive or zero voltages were applied to word line 22, coupling gate 26, and floating gate 24 to perform read, program, and erase operations. The prior art did not apply negative voltages for these operations.
One object of the present invention is the disclosure of a non-volatile memory cell device that applies a negative voltage to word line 22, coupling gate 26, and/or floating gate 24 during read, program, and/or erase operations.